1. Field of the Invention
The present invention relates to a method for generating a layout pattern, and more particularly, to a method for generating a layout pattern including mandrel patterns by using anchor bar patterns.
2. Description of the Prior Art
As the size of the field effect transistors (FETs) becomes smaller continuously, the conventional planar field effect transistor has difficulty in development because of the manufacturing limitations. Therefore, for overcoming the manufacturing limitations, the non-planar transistor technology such as Fin Field effect transistor (FinFET) technology is developed to replace the planar FET and becomes a development trend in the related industries.
Generally, patterned structures such as fin structures in the FinFET may be manufactured by a sidewall image transfer (SIT) technology through the following processes. First, a layout pattern including patterned structures to be formed is inputted into a computer system and is modified through suitable calculation for generating corresponding mandrel patterns. The mandrel patterns are then defined in a mask, and patterned structures manufactured by the SIT technology may be obtained by performing photolithography processes with the mask and corresponding etching processes. However, the layout patterns of the fin structures in each cluster regions generally have to modified through calculations separately for generating required mandrel patterns because the fin structures in each of the cluster regions on a chip maybe not designed to be aligned with one another (generally called as “not on global grid”), and the required calculation time is increased accordingly. For handling more complicated patterned structures, an improved method for generating the layout pattern is demanded for accelerating the process and calculation time.